In a thin film device, such as a multichip carrier having a substrate over which a plurality of thin film wiring layers are sequentially formed, inspection of each thin film layer as it is fabricated is often not economically viable due at least to the large number of fine geometry wiring paths which are distributed over the relatively much large surface area of each of the thin film layers. Thus, the conventional practice is to test the full stack of thin film wiring for functionality only from a top surface. If a defect is detected, the repair can be accomplished by using either wire bonded discrete wires or laser assisted techniques, the repair typically being limited to surface areas which are accessible between the integrated circuit chips which are bonded to the top surface. One significant disadvantage of both of these repair methods is that they require the dedication of significant areas of the surface. Also, significant portions of the internal wiring may be inaccessible from the top surface, these portions being essentially unrepairable. In that the costs associated with the fabrication of the carrier have already been substantially incurred by the time the final testing cycle is initiated, it can be realized that discarding an unrepairable complex carrier is not economically advantageous.
Process monitors are known in integrated circuit wafer manufacturing; however these monitors are generally not suitable for use with multichip carriers manufacturing methodologies for a number of reasons.
For example, in the case of semiconductor wafer fabrication the process monitors measure active device characteristics such as V.sub.BE, .beta., r.sub.b, etc. while in a thin film layer region the critical parameters relate to the integrity of the connectivity between layers. Also, certain thin film electrical characteristics, such as dielectric constant, metal resistivity and via contact resistance, affect the thin film region performance. For example, the dielectric constant affects the transmission line impedance, propagation delay and coupled noise. The dielectric constant also yields information relating to moisture or solvent trapping, improper curing cycles, etc.
Another distinction between semiconductor wafer fabrication monitors and those required for thin film wiring fabrication is that for the wafer, for each fabrication step, active device and even personalization wiring require unique and substantially unrelated processing techniques. In the case of a multichip carrier to which this invention is especially applicable the thin film wiring is fabricated by repeating substantially the same process steps for each layer in the sequentially, built thin film region with the same metallurgy and ground rules. Also, in the case of thin film wiring fabrication, if a problem could be detected by a process monitor in one of the initial layers, such as too high a resistivity for a bottom power plane, the subsequent processing step conditions or tooling could be altered to compensate for the problem in order to build the subsequent layers properly.
In the case of thin film devices it is desirable to detect catastrophic processing failures such that the build of the full stack of thin film layers can be halted. In the non-analogous case of semiconductor wafer fabrication a monitor which indicates a catastrophic process failure also generally indicates that the wafer is unusable. However, in a hybrid module having thin film layers, the defective thin film layers can be lapped off the top of the underlying substrate and thin film processing can restart on the polished substrate surface.
Another distinction is that tool set-up monitors are not used in conventional chip fabrication because in-situ repair or engineering changes (EC) are not practiced on wafers. Malfunctioning chips are usually discarded. However, costly multichip carriers that may require months to be completed cannot be as readily discarded. The facilitation of repair/EC techniques is thus essential. As such, it would be desirable that tool monitors allow the set-up of parameters for laser tooling in order to prevent damage to the active area of the module and to obtain the best conditions for optimum electrical performance. One advantageous position for such tooling set-up would be at sites which do not interfere in any way with the densely wired thin film active wiring region, such as sites disposed peripheral to the active thin film wiring areas. These sites preferably also providing sites for wire bonding and decal ultrasonic bonding EC activities.
Although thin film sequential processing is practiced presently for fabricating personalization layers for logic or array chips on silicon wafers this application is not analogous to that of thin film multichip carriers in that dedicated chip sites are available for placement of process and/or tooling monitors, these medicated chip sites being denoted to process/yield monitoring. Also, each such dedicated chip site on the wafer correspondingly reduces the number of useable devices which can be fabricated on the wafer with a consequent reduction in overall wafer yield.
In the case of the multichip carrier the entire active thin film wiring area is occupied by dense inter-chip wiring and contains no chip sites which can be dedicated to providing such process/tooling monitor sites.
Based on the foregoing it can be realized that in order to fabricate multichip carriers having thin film layers of significant wiring density, in a reliable and cost effective manner, that appropriate fabrication process monitors are an essential requirement. However, this need has remained unfulfilled until the invention of the thin film process monitors which are described in detail below.